3-dimensional nonvolatile memory device and method of manufacturing the same

ABSTRACT

The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 10-2011-0109479, filed on Oct. 25, 2011, the disclosureof which is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and a method ofmanufacturing the same. More specifically, the present invention relatesto a 3-dimensional nonvolatile memory device and a method ofmanufacturing the same.

A nonvolatile memory device is a kind of memory device, which is capableof intactly retaining stored data without power supply. As atwo-dimensional memory device manufactured as a single layer on asilicon substrate may be reaching a technical limit for increasingintegration density, a three-dimensional nonvolatile memory device,which includes memory cells vertically stacked on a silicon substratehas been proposed recently.

Hereinafter, some concerns in conventional three-dimensional nonvolatilememory devices will be described in detail, with reference to thedrawings.

FIG. 1 is a cross-sectional view of a conventional 3-dimensionalnonvolatile memory device.

Referring to FIG. 1, the conventional 3-dimensional nonvolatile memorydevice may include channels CH protruding from a substrate 10 and aplurality of memory cells MC stacked along the channels CH. Also, thememory device may further include a lower selection gate LSG formedunder the plurality of memory cells MC and an upper selection gate USGformed on the plurality of memory cells MC. Bit lines BL may be providedon the upper selection gate USG. The bit lines BL are connected to thechannels CH. In the above-described structure, a plurality of memorycells MC connected in series between the lower selection gate LSG andthe upper selection gate USG may constitute one string STRING, which maylocate vertically on the substrate 10.

In FIG. 1, reference numerals 11, 14, and 17 denote interlayerinsulating layers. A reference numeral 12 denotes a lower selectionline. Reference numeral 15 denotes a word line. A reference numeral 18denotes an upper selection line. Also, reference numerals 13 and 19denote gate insulating layers. A reference numeral 16 denotes a chargeblocking layer, a charge trap layer, and a tunnel insulating layer.

A method of forming the memory cells CH is briefly described. Aplurality of conductive layers 15 and a plurality of interlayerinsulating layers 14 may be alternately formed and etched in order toform trenches. Thereafter, a charge blocking layer, a charge trap layer,and a tunnel insulating layer 16 may be formed on inner walls of thetrenches. A channel layer may be formed in the trenches. Due to theabove-described manufacturing process, charge trap layers of theplurality of memory cells MC stacked along the channels CH may beconnected to one another.

Here, the charge trap layer may serve as a substantial data storagewhere data is stored by injecting or emitting charges. In theconventional structure where the charge trap layers of the memory cellsMC are connected to one another, charges stored in one memory cell MCmay be moved or transported to another memory cell MC so that storeddata may be changed or damaged.

SUMMARY OF THE INVENTION

The present invention is directed to a 3-dimensional nonvolatile memorydevice, which is capable of improving data retention characteristics anda method of manufacturing the same.

One aspect of the present invention provides a nonvolatile memory deviceincluding plural control gates stacked on a substrate, plural firstchannels, configured to penetrate the control gates, and plural memorylayer patterns, each located between the control gate and the firstchannel, configured to respectively surround the first channel, whereinthe memory layer patterns are isolated from one another.

Another aspect of the present invention provides a method ofmanufacturing a nonvolatile memory device. The method includesalternately forming first material layers and second material layers,etching the first material layers and the second material layers to formfirst trenches, etching the second material layers exposed in the firsttrenches, forming a charge trap layer along inner surfaces of the firsttrenches in which the second material layers are etched, forming achannel layer on the charge trap layer to form first channels havingprotrusions protruding between the stacked first material layers,etching the first material layers and the second material layers to formslits between adjacent first trenches, etching the charge trap layerexposed to inner walls of the slits to isolate the charge trap layer ofstacked memory cells from one another, and forming an insulating layerin the slits in which the charge trap layer is etched.

Another aspect of the present invention provides a method ofmanufacturing a nonvolatile memory device. The method includesalternately forming conductive layers and first sacrificial layers;etching the conductive layers and the first sacrificial layers to formfirst trenches; forming a charge trap layer along inner surfaces of thefirst trenches; forming a channel layer on the charge trap layer to formfirst channels protruding from a substrate; etching the conductivelayers and the second sacrificial layers to form slits between adjacentfirst trenches; etching the first sacrificial layers exposed in theslits to expose the charge trap layer; etching the charge trap layerexposed in the slits to isolate the charge trap layer of stacked memorycells from one another; forming junctions in the first channels exposedby etching the charge trap layer; and forming an insulating layer in theslits.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments thereof with reference to theattached drawings in which:

FIG. 1 is a cross-sectional view of a structure of a conventional3-dimensional nonvolatile memory device;

FIGS. 2A through 2F are cross-sectional views illustrating a method ofmanufacturing a 3-dimensional nonvolatile memory device according to afirst exemplary embodiment of the present invention;

FIGS. 3A through 3D are cross-sectional views illustrating a method ofmanufacturing a 3-dimensional nonvolatile memory device according to asecond exemplary embodiment of the present invention;

FIGS. 4A through 4D are cross-sectional views illustrating a method ofmanufacturing a 3-dimensional nonvolatile memory device according to athird exemplary embodiment of the present invention;

FIG. 5 is a cross-sectional view of a structure of a 3-dimensionalnonvolatile memory device including memory cells according to the firstexemplary embodiment;

FIG. 6 is a cross-sectional view of a structure of a 3-dimensionalnonvolatile memory device including memory cells according to the secondembodiment;

FIG. 7 is a cross-sectional view of a structure of a 3-dimensionalnonvolatile memory device including memory cells according to the thirdexemplary embodiment;

FIG. 8 is a configuration diagram of a memory system according to anexemplary embodiment of the present invention; and

FIG. 9 is a configuration diagram of a computing system according to anexemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. In the drawings, thicknesses and intervalsare illustrated for brevity and may be exaggerated with respect toactual physical thicknesses.

Descriptions of well-known components and processing techniquesirrelevant to the embodiments of the present invention may be omitted.The same or similar numbers may be described with reference to otherdrawings even if they are neither mentioned nor described in thecorresponding drawing. Also, even elements that are not denoted byreference numbers may be described with reference to other drawings.

FIGS. 2A through 2F are cross-sectional views illustrating a method ofmanufacturing a 3-dimensional nonvolatile memory device according to afirst exemplary embodiment of the present invention. For brevity, only amemory cell region is illustrated in FIGS. 2A through 2F.

Referring to FIG. 2A, a plurality of first material layers 21 and aplurality of second material layers 22 may be alternately formed.

Here, forming the first material layers 21 may be to form control gates,while the second material layers may be formed to form interlayerinsulating layers configured to isolate stacked control gates from oneanother. Accordingly, the numbers of the stacked first material layers21 and second material layers 22 may be determined by the number ofmemory cells to be stacked.

The first material layers 21 and the second material layers 22 may beformed of materials having different etch selectivity ratios. Herein,the first material layers 21 may be a conductive layer for controlgates, while the second material layers 22 may be a sacrificial layer.Otherwise, the first material layers 21 may be a sacrificial layer,while the second material layers 22 may be an interlayer insulatinglayer. In the first embodiment, the first material layers 21 aresacrificial layers such as a nitride layer. The second material layers22 are interlayer insulating layers, such as an oxide layer.

Thereafter, the plurality of first material layers 21 and the pluralityof second material layers 22 may be etched to form a plurality of firsttrenches. The plurality of second material layers 22 exposed to innerwalls of the first trenches may be etched by a partial thickness.

Thereafter, a memory layer 23 may be formed along inner surfaces of thefirst trenches formed by a process of etching the plurality of secondmaterial layers 22 by the partial thickness. Here, the memory layer 23may include a charge blocking layer, a charge trap layer, and a tunnelinsulating layer. However, according to an embodiment, only the chargetrap layer and the tunnel insulating layer, except for the chargeblocking layer, may be formed.

Subsequently, a channel layer may be formed on the memory layer 23,thereby forming first channels 24 through the stacked first materiallayers 21 and second material layers 22. Here, forming the channel layeron the inner walls of the first trenches may be to fill into regionsobtained by a process of etching the plurality of second material layers22 by the partial thickness. Accordingly, the first channels 24 mayinclude a plurality of protrusions ‘A’, each protruding between thestacked first material layers 21.

Here, forming the channel layer to such a thickness may be to completelyfill central regions of the first trenches or open the central regionsof the first trenches. When the central regions are opened, i.e., thechannel layer does not pack into the first trenches, an insulating layer25 may be formed on the opened central regions.

Referring to FIG. 2B, the plurality of first material layers 21 and theplurality of second material layers 22 may be etched to form slits Sbetween adjacent first channels 24. In FIG. 2B, a reference numeral 21Adenotes etched first material layers. A reference numeral 22A denotesetched second material layers. Although FIG. 2B illustrates that theplurality of second material layers 22A partially remain after a step offorming the slits ‘S,’ the plurality of second material layers 22 may bewholly removed.

Referring to FIG. 2C, the memory layer 23 may be exposed by removing theremaining second material layers 22A. The memory layer 23 exposed in theslits S may be etched (refer to reference character “B”). In this case,since the protrusions ‘A’ locates between the first material layers 21A,the collapse of the first material layers 21A may not occur. Further,the memory layer 23 may be easily etched.

As a result, the memory layer 23 may be patterned into a plurality ofmemory layer patterns 23A. The charge trap layers of the memory cellsstacked along the first channels 24 may be isolated from one another.Accordingly, the transport of charges between the stacked memory cellsmay not occur.

Although not shown in FIG. 2C, impurities may be implanted into theprotrusions ‘A’ of the first channels 24 exposed by etching the memorylayer 23, thereby forming junctions. In this case, adjusting a dopingdepth of the impurities may control the depth of the junctions.

Referring to FIG. 2D, the plurality of first material layers 21A exposedin the slits ‘S’ may be removed to form a plurality of control gateregions. In this case, the plurality of protrusions ‘A’ may function asmolds for control gates. Regions between the protrusions may become thecontrol gate regions.

Thereafter, depositing a conductive layer in the plurality of controlgate regions may be to form a plurality of control gates 28. Forexample, a first metal layer 26 may be formed along the inner surfacesof the slits ‘S’ including the plurality of control gate regions,Forming second metal layer 27 on the first metal layer 26 may be to fillthe control gate regions. Here, the first metal layer 26 may be abarrier metal layer. The second metal layer 27 may be a gap-fill metallayer. Afterwards, the second metal layer 27 formed on the inner wallsof the slits ‘S’ except the plurality of control gate regions may beetched by a combination of a wet etching process and a dry etchingprocess. Thereafter, a cleaning process may etch the first metal layer26 formed on the inner walls of the slits S except the plurality ofcontrol gate regions. As a result, the conductive layer formed in theplurality of control gate regions may be separated into the plurality ofcontrol gates 28.

When only the charge trap layer and the tunnel insulating layer areformed during the formation of the memory layer 23 as described above, acharge blocking layer may be formed before forming the control gates 28.

Referring to FIG. 2E, a plurality of protrusions protruding between thestacked control gates 28 may be etched. In FIG. 2E, a reference numeral24A denotes first channels having etched protrusions.

When the protrusions are etched, the effective length of a channel ofeach of the memory cells may be reduced. Naturally, the protrusions maybe partially etched or may not be etched but remain. In addition, afteretching the protrusions, junctions may be formed in the first channels24A between the stacked control gates 28.

Referring to FIG. 2F, an insulating layer may be formed in the slits Sin which the plurality of protrusions are etched. Thus, a plurality ofmemory cells stacked along the first channels 24A may be formed. Inparticular, according to the first embodiment, angled C shaped memorylayer patterns 23A may respectively surround the control gates 28. Thatis, the memory layer patterns 23A may locate between the first channels24A and the plurality of control gates 28 to surround top and bottomsurfaces of the plurality of control gates 28. Accordingly, theplurality of memory cells stacked along the first channels 24A mayinclude the isolated charge trap layers, respectively.

In the first embodiment, the first material layers 21 may be formed as aconductive layer for control gates, such as a doped polysilicon (dopedpoly-Si) layer or a doped amorphous silicon layer, while the secondmaterial layer 22 may be formed as a sacrificial layer such as anundoped poly-Si layer or an undoped amorphous silicon layer. Here, theterm “doped” means being doped with a dopant, such as boron (B), and“undoped” means being not doped with a dopant.

In this case, after performing the processes described with reference toFIGS. 2A through 2C, an insulating layer may be formed in the slits ‘S.’The formation the memory cells stacked along the first channels 24 maybe completed. In this case, before forming the insulating layer, theplurality of first material layers 21 exposed in the slits 5 may besilicided. For example, the silicidation of the first material layers 21may include forming a metal layer in the slits ‘S,’ siliciding the firstmaterial layers 21 using an annealing process, and removing theremaining metal layer. Before forming the insulating layer, junctionsmay be formed in the protrusions protruding between the stacked firstmaterial layers 21, the protrusions may be etched, or junctions may beformed in the first channels 24 between the stacked first materiallayers 21 after etching the protrusions.

FIGS. 3A through 3D are cross-sectional views illustrating a method ofmanufacturing a 3-dimensional nonvolatile memory device according to asecond embodiment of the present invention.

The second embodiment pertains to a method of forming control gates byforming additional molds after etching protrusions of first channels.Hereinafter, a description of the same processes as in the firstembodiment will be omitted.

Referring to FIG. 3A, first channels 33 including a plurality ofprotrusions may be formed through a plurality of first material layers31. A memory layer 32 may locate between the first channels 33 and aplurality of control gates 31 to surround the first channels 33. Slits‘S’ may be formed between adjacent first channels 34. Here, depositingthe first material layers 31 may be to form a sacrificial layer, such asa nitride layer, while the second material layers 32 may be formed as aninterlayer insulating layer, such as an oxide layer.

Referring to FIG. 3B, the plurality of protrusions of the first channels33, which may protrude between the stacked first material layers 31, maybe etched. In this case, the memory layer 32 configured to surround theplurality of protrusions may be etched together. Here, regions where theplurality of protrusions and the memory layer 32 are etched(hereinafter, mold regions M) may be required for forming molds used toform subsequent control gates 31.

In this case, the memory layer 32 may be patterned into a plurality ofmemory layer patterns 32A, which may be respectively interposed in anI-shape between the first channels 33A and the first material layers 31.Accordingly, each memory layer pattern 32A may be separated with apredetermined distance to prevent charges from moving between the memorycells.

Furthermore, the protrusions of the first channels 33A may be removed sothat channels of the memory cells do not surround control gates but beformed in straight shapes. Thus, the channel effective length of thememory cells may decrease.

Although not shown in FIG. 3B, after etching the plurality ofprotrusions and the memory layer 32 configured to surround theprotrusions, junctions may be formed by implanting impurities into thefirst channels 33A exposed between the stacked first material layers 31.

Referring to FIG. 3C, the mold regions ‘M’ may be filled with aninsulating layer, such as an oxide layer. Here, insulating layers formedin the mold regions ‘M’ may be molds 35 for forming control gates.

Thereafter, the plurality of first material layers 31 may be removed toform a plurality of control gate regions. Here, the plurality of controlgate regions may be isolated from one another by the molds 35.

Referring to FIG. 3D, a conductive layer may be formed in the pluralityof control gate regions to form a plurality of control gates 38. Each ofthe control gates 38 may include a first metal layer 36 and a secondmetal layer 37. The first metal layer 36 may be a barrier metal layer,while the second metal layer 37 may be a gap-fill metal layer.

Thereafter, an insulating layer 39 may be formed in the slits ‘S’ inwhich the plurality of control gates 38 are formed. The formation of thememory cells stacked along the first channels 33A may be completed.

In the second embodiment, the first material layers 31 may be aconductive layer for control gates, while the second material layers 32may be a sacrificial layer. In this case, after performing the processesdescribed with reference to FIGS. 3A and 3B, an insulating layer may beformed in the slits 5, and the formation of memory cells stacked alongthe first channels 33A may be completed. In this case, before formingthe insulating layer, the plurality of first material layers 31 exposedto inner walls of the slits S may be silicided.

FIGS. 4A through 4D are cross-sectional views illustrating a method ofmanufacturing a 3-dimensional nonvolatile memory device according to athird exemplary embodiment of the present invention. In FIGS. 4A to 4D,only a memory cell region is illustrated for brevity.

Referring to FIG. 4A, a plurality of first material layers 41 and aplurality of second material layers 42 may be alternately formed. Here,the first material layers 41 may be conductive layers for control gates,while the second material layers 42 may be sacrificial layers.

Thereafter, etching the plurality of first material layers 41 and theplurality of second material layers 42 may form a plurality of firsttrenches. A memory layer 43 may be formed on inner walls of the firsttrenches. Here, the memory layer 43 may include a charge blocking layer,a charge trap layer, and a tunnel insulating layer.

Thereafter, a channel layer may be formed on the memory layer 43 to formfirst channels 44 passing through the plurality of first material layers41 and the plurality of second material layers 42. In this case, whenthe first channels 44 have a structure to open central regions of thefirst channels 44, deposting an insulating layer 45 may to fill in theopen central regions.

Referring to FIG. 4B, the plurality of first material layers 41 and theplurality of second material layers 42 may be etched to form slits ‘S’between adjacent first channels 44. Thereafter, the plurality of secondmaterial layers 42 exposed in the slits ‘S’ may be etched.

Thereafter, etching the plurality of second material layers 42 may be toexpose a part of the memory layer 43. In this case, etching the exposedmemory layer may split the memory layer 43 into a plurality of memorylayer patterns 43A, which may locate only between each first channel 44and each first material layers 41.

Referring to FIG. 4C, impurities may be implanted into the firstchannels 44 exposed between the memory layer patterns 43A, therebyforming junctions 46. In an example, the junctions 46 may be formed byimplanting ions in a lateral direction. In another example, theformation of the junctions 46 may include forming doped third materiallayers (not shown) and diffusing impurities of the third material layersinto the exposed first channels 44 using an annealing process. In thiscase, after forming the junctions 46, the third material layers may beremoved.

As a result, the first channels 44A may include a plurality of junctions46 formed between the stacked first material layers 41. The junctions 46may be respectively disposed between the stacked memory cells.Accordingly, the junctions 46 may be provided in the first channels 44Abetween the stacked memory cells so that the memory device may be drivenin an enhanced mode.

Referring to FIG. 4D, an insulating layer 47 may be formed in the slits‘S’ in which the junctions 46 are formed, thereby completing theformation of the memory cells stacked along the first channels 44A.

FIG. 5 is a cross-sectional view of a structure of a 3-dimensionalnonvolatile memory device including memory cells according to the firstembodiment.

Referring to FIG. 5, the memory device may include an interlayerinsulating layer 52 formed on a substrate 51, a pipe gate 53 formed onthe interlayer insulating layer 52, a second channel 55 formed in thepipe gate 53 and connected to a pair of first channels 24A. Here, onepair of first channels 24A and one second channel 55 may be connected ina U-shape and constitute one string channel CH. Also, the memory devicemay further include a gate insulating layer 54 configured to surroundthe second channel 55.

The gate insulating layer 54 may be formed during formation of a memorylayer 23, while the second channel 55 may be formed during the formationof the first channels 24A.

For example, before forming a plurality of material layers and aplurality of second material layers, the pipe gate 53 may be etched toform a second trench in a position connected to a pair of firsttrenches, and a sacrificial layer may be formed in the second trench.After forming the plurality of first trenches, the sacrificial layer maybe removed to form a U-shaped trench including a pair of first trenchesand a second trench. Thereafter, as described in the first embodiment,the memory layer 23 and a channel layer may be formed. In this case, thememory layer 23 and the channel layer may be formed in the U-shapedtrench.

When the memory cells are formed using the above-described method, thememory layer 23 surrounding the second channel 55 may be separated fromthe memory layer 23 surrounding the first channels 24A during theetching of the memory layer 23 to form the plurality of memory layerpatterns 23A. Here, the memory layer patterns 23A surrounding the firstchannels 24A may respectively surround a plurality of control gates 28in an angled C-shape. The memory layer patterns 23A might be separatedfrom one another. Also, the memory layer patterns 23A surrounding thesecond channel 55 may surround sidewalls and bottom surface of thesecond channel 55 in a U-shape, and serve as the gate insulating layer54.

Therefore, according to the present invention, charge trap layers of thestacked memory cells may be isolated from one another. The memory layerpattern 23A of the lowermost memory cell may be separated from the gateinsulating layer 54 of the pipe gate 53.

After forming the control gates 28, connections between the firstchannels 24A and the second channel 55 exposed in a slit ‘S’ may beetched during the etching of protrusions of the first channels 24.Accordingly, an etching process may be controlled to prevent the firstchannels 24A from being separated from the second channel 55 due to thecomplete etching of the connections between the first channels 24A andthe second channel 55.

Alternatively, a protection layer may be formed on bottom surfaces ofslits ‘S’ prior to a protrusion etching process. For example, theprotection layer may have substantially the same height with the controlgate of the lowermost memory cell, in order to cover the connectionsbetween the first channels 24A and the second channel 55 through thebottom surfaces of the slits ‘S.’ On the other hands, an etching depthfor the slits ‘S’ may be controlled in a range of completely exposingthe first material layers 21 but not etching the lowermost secondmaterial layer 22. In this case, the connections between the firstchannels 24A and the second channel 55 may be not exposed during theprotrusion etching process. In addition, the width of the pipe trenchmay be reduced not to expose the connections between the first channels24A and the second channel 55.

Although not shown in FIG. 5, after filling the second trench with thesacrificial layer, the pipe gate 53 may be further formed. In this case,the gate insulating layer 54 formed on the second channel 55 may bemaintained. The gate insulating layer 54 may be maintained using thesame method as the above-described method of preventing the etching ofthe connections between the first channels 24A and the second channel55. By further forming the pipe gate to cover the second channel 54, acell current supplied to the second channel 54 may be improved toimprove the performance of the memory device.

FIG. 6 is a cross-sectional view of a structure of a 3-dimensionalnonvolatile memory device including memory cells according to the secondexemplary embodiment.

Referring to FIG. 6, the memory device may include an interlayerinsulating layer 62 formed on a substrate 61, a pipe gate 63 formed onthe interlayer insulating layer 62, a second channel 65 formed in thepipe gate 63 and connected to a pair of first channels 24A, and a gateinsulating layer 64 configured to surround the second channel 65.

One pair of first channels 24A and one second channel 65 may beconnected in a U-shape and constitute one string channel CH. Also,memory layer patterns 23A may be respectively interposed in an I-shapebetween a plurality of control gates and the first channels 24A.

FIG. 7 is a cross-sectional view of a structure of a 3-dimensionalnonvolatile memory device including memory cells according to the thirdexemplary embodiment.

Referring to FIG. 7, the memory device may include an interlayerinsulating layer 72 formed on a substrate 71, a pipe gate 73 formed onthe interlayer insulating layer 72, a second channel 75 formed in thepipe gate 73 and connected to a pair of first channels 74A, and a gateinsulating layer 74 configured to surround the second channel 75.

One pair of first channels 24A and one second channel 75 may beconnected in a U-shape and constitute one channel CH. Also, memory layerpatterns 43A may be respectively interposed in an I-shape between aplurality of control gates and the first channels 24A. In addition,junctions 46 may be disposed in first channels 44A between stackedmemory cells.

FIG. 8 is a configuration diagram of a memory system 100 according to anexemplary embodiment of the present invention.

Referring to FIG. 8, the memory system 100 may include a nonvolatilememory device 120 and a memory controller 110.

The nonvolatile memory device 120 may be formed to have theabove-described cell structure. Also, the nonvolatile memory device 120may be a multi-chip package (MCP) including a plurality of flash memorychips.

The memory controller 110 may be configured to control the nonvolatilememory device 120 and include a static random access memory (SRAM) 111,a central processing unit 112, a host interface 113, an error correctioncode (ECC) unit 114, and a memory interface 115. The SRAM 111 may beused as an operation memory of the CPU 112. The CPU 112 may perform theoverall control operation for exchanging data of the memory controller110. The host interface 112 may include a data exchange protocol of ahost connected to the memory system 100. Further, the ECC unit 114 maydetect and correct errors in data read from the nonvolatile memorydevice 120. The memory interface 115 may interface with the nonvolatilememory device 120. In addition, the memory controller 110 may include aread context manager (RCM) configured to store code data required forinterfacing with the host.

The memory system 100 having the above-described construction may be amemory card or solid-state disk (SSD) having operational characteristicsof both the nonvolatile memory device 120 and the memory controller 110.For example, when the memory system 100 is an SSD, the memory controller110 may communicate with the outside (e.g., the host) through one ofvarious interface protocols, such as a universal serial bus (USB), a manmachine communication (MMC), a peripheral component interconnect-express(PCI-E), a serial advanced technology attachment (SATA), a paralleladvanced technology attachment (PATA), a small computer system interface(SCSI), an enhanced small device interface (ESDI), or an intelligentdrive electronics (IDE).

FIG. 9 is a configuration diagram of a computing system 200 according toan exemplary embodiment of the present invention.

Referring to FIG. 9, the computing system 200 according to theembodiment of the present invention may include a CPU 220, a randomaccess memory (RAM) 230, a user interface 240, a modem 250, and a memorysystem 210, which may be electrically connected to each other through asystem bus 260. When the computing system 200 is a mobile device, thecomputing system 200 may further include a battery configured to supplyan operating voltage to the computing system 200. The computing system200 may further include an application chipset, a camera image processor(CIS), and a mobile dynamic random access memory (mobile DRAM).

As described with reference to FIG. 8, the memory system 210 may includea nonvolatile memory 212 and a memory controller 211.

According to the present invention, charge trap layers of stacked memorycells may be isolated from one another. Accordingly, interferencesbetween selection gates as well as between memory cells may be reduced,thereby improving the efficiency of program, erase, and read operations.Furthermore, junctions may be formed in channels between stacked controlgates so that a memory device may be driven in an enhanced mode.

In the drawings and specification, there have been disclosed typicalexemplary embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation. As for the scope of the invention, it is tobe set forth in the following claims. Therefore, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

What is claimed is:
 1. A nonvolatile memory device, comprising: pluralcontrol gates stacked on a substrate; plural first channels, configuredto penetrate the control gates; and plural memory layer patterns, eachlocated between the control gate and the first channel, configured torespectively surround the first channel, wherein the memory layerpatterns are isolated from one another.
 2. The device of claim 1,wherein the first channel includes protrusions configured to protrudebetween the stacked control gates.
 3. The device of claim 1, wherein thefirst channel includes plural junctions, located between the stackedcontrol gates.
 4. The device of claim 1, wherein the memory layerpattern surrounds top and bottom surfaces of the control gate.
 5. Thedevice of claim 1, wherein the memory layer pattern is confined betweenthe first channel and the control gate.
 6. The device of claim 1,further comprising: a pipe gate formed on the substrate; and a secondchannel, formed in the pipe gate, configured to connect a pair of firstchannels.
 7. A method of manufacturing a nonvolatile memory device,comprising: alternately forming first material layers and secondmaterial layers; etching the first material layers and the secondmaterial layers to form first trenches; etching the second materiallayers exposed in the first trenches; forming a charge trap layer alonginner surfaces of the first trenches in which the second material layersare etched; forming a channel layer on the charge trap layer to formfirst channels having protrusions protruding between the stacked firstmaterial layers; etching the first material layers and the secondmaterial layers to form slits between adjacent first trenches; etchingthe charge trap layer exposed in the slits to isolate the charge traplayer of stacked memory cells from one another; and forming aninsulating layer in the slits in which the charge trap layer is etched.8. The method of claim 7, wherein when the second material layers remainon the inner walls of the slits, the etching of the charge trap layer isperformed after removing the remaining second material layers.
 9. Themethod of claim 7, further comprising, forming junctions in theprotrusions exposed between the first material layers after the etchingof the charge trap layer.
 10. The method of claim 7, further comprising,etching the protrusions exposed between the first material layers afterthe etching of the charge trap layer.
 11. The method of claim 10,further comprising, forming junctions in the first channels exposedbetween the first material layers after the etching of the protrusions.12. The method of claim 7, further comprising: forming control gateregions by removing the first material layers exposed in the slits,after the etching of the charge trap layer; and forming control gates byforming a conductive layer in the control gate regions.
 13. The methodof claim 12, wherein the forming of the control gates comprises: forminga first metal layer and a second metal layer in the slits in which thecontrol gate regions are formed; etching the second metal layer formedin the slits except the control gate regions, using a combination of awet etching process and a dry etching process; and etching the firstmetal layer formed in the slits except the control gate regions, using acleaning process.
 14. The method of claim 7, wherein the etching of thecharge trap layer comprises etching the protrusions and the charge traplayer surrounding the protrusions to form mold regions.
 15. The methodof claim 14, further comprising: filling the mold regions with aninsulating layer to form molds required for forming the control gates,after the etching of the charge trap layer; removing the first materiallayers to form the control gate regions; and forming a conductive layerin the control gate regions to form the control gates.
 16. The method ofclaim 15, wherein the forming of the control gates comprises: forming afirst metal layer and a second metal layer in the slits in which thecontrol gate regions are formed; etching the second metal layer formedin the slits except the control gate regions, using a combination of awet etching process and a dry etching process; and etching the firstmetal layer formed in the slits except the control gate regions, using acleaning process.
 17. The method of claim 7, further comprising: etchinga pipe gate to form a second trench in a position connected to a pair offirst trenches, before forming the first material layers and the secondmaterial layers; forming a sacrificial layer in the second trench; andremoving the sacrificial layer after the forming of the first trenches.18. The method of claim 7, wherein the first material layers and thesecond material layers are formed of materials having a high etchselectivity ratios against each other.
 19. A method of manufacturing anonvolatile memory device, comprising: alternately forming conductivelayers and first sacrificial layers; etching the conductive layers andthe first sacrificial layers to form first trenches; forming a chargetrap layer along inner surfaces of the first trenches; forming a channellayer on the charge trap layer to form first channels protruding from asubstrate; etching the conductive layers and the second sacrificiallayers to form slits between adjacent first trenches; etching the firstsacrificial layers exposed in the slits to expose the charge trap layer;etching the charge trap layer exposed in the slits to isolate the chargetrap layer of stacked memory cells from one another; forming junctionsin the first channels exposed by etching the charge trap layer; andforming an insulating layer in the slits.
 20. The method of claim 19,further comprising: forming a pipe gate before the alternately formingof the conductive layers and the first sacrificial layers; etching thepipe gate to form a second trench in a position connected to a pair offirst trenches; forming a second sacrificial layer in the second trench;and removing the second sacrificial layer after the forming of the firsttrenches.